In August 2007 AAI partnered with eASIC Corporation to support increasing demand for Structured ASIC in Israel. eASIC offers a breakthrough Structured ASIC devices that reduce the overall fabrication cost and time of customized silicon devices. Through employing a unique combination of FPGA like logic-cells and via-layer customizable routing, teams of AAI and eASIC enable customers to develop Structured ASICs with zero mask charges and no minimum order quantity, in 4 weeks turnaround. AAI enhanced its services' portfolio by providing design, technical and sales support to customers using eASIC's Structured ASIC devices in Israel.
 

eASIC Structured ASIC presents a perfect combination of FPGA and ASIC

 
 
 
 
The family of eASIC's devices is manufactured on a 90nm CMOS process, using eASIC's patented customization technology. The Structured ASIC is offered along with a soft IP portfolio including 175MHz ARM926EJ, PIP-AMBA, H.264, PCI Express, DDR2 and Ethernet MAC among others.
 
 

Major Features of eASIC's Structured ASIC

  • 350 MHz system performance
  • 6 base arrays from 350K to 5M Gates
  • Up to 5.6Mb of block RAM
  • Multi-voltage core (1.2V or 1.3V)
  • Up to 790 user I/Os
  • Flipchip & wirebond packages
  • 90 nm Fujitsu process technology
 

Major Benefits of eASIC's Structured ASIC

  • No mask charges
  • No minimum order quantity
  • Logic/Memory tradeoff
  • Configurable I/O
  • Late stage Via and bitstream programmable
  • Tape-out to chips in hand <4 weeks
 

List of Available Devices

 

Structured ASIC Background

 
The need for an alternative ASIC solution emerged as in deep-submicron design environment the manufacturing complexity increased exponentially and hence the NRE cost became skyrocketing. eASIC’s innovative fabric is aimed at coping with today’s design challenges by providing affordable customization, ease-of-design and rapid development of ASIC, System-on-Chip and product derivatives.
 
While the customization technology is innovative and protected by broad patents, the design implementation and device fabrication are performed using conventional electronic design flow and standard manufacturing processes.
 
Structured ASICs in general are based on a predefined logic fabric - in essence, an array of pre-built logic cells and an arrangement of configurable memory blocks. This array can be fabricated up through the first few metal layers as if it were a standard product, almost as a cross between an FPGA and a gate array. Then the base wafers can be warehoused, waiting for final customization per a customer order. A customer design, meanwhile, is accepted at the register-transfer or netlist level and mapped onto the logic cells and the memory blocks. The wafers are pulled from inventory, the upper metal layers completed to implement the customer's design and the finished wafers treated from thereon as any other ASIC. eASIC took this concept further to develop a more innovative Structured ASIC solution in which all metal layers are standard, pre-fabricated and the customization is performed only by one or two via-layers.

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