Experienced Back-End Engineer

 Requirements:

  • BSc. in Electrical Engineering (from known university)
  • Minimum 2 years of experience – Must!

Knowledge and experience in:

  • Floor plan and Place & Route
  • Timing Closure & debug, STA
  • Clock Tree Synthesis
  • Power Grid Analysis
  • LVS/DRC debug
  • Experience with DFT - Advantage

Experience with ICC – Advantage

 

Experienced ASIC Project leader

Requirements:

  • BSc. in Electrical Engineering (from known university)
  • Minimum 5 years of experience – Must!
  • Technical management experience – Advantage

 

Knowledge and experience in:

  • Floor plan and Place & Route, Block & Top level
  • Timing Closure & debug, STA, SDC insertion and analysis.
  • Clock Tree Synthesis
  • Power Grid Analysis
  • LVS/DRC Debug
  • DFT & ATPG methodologies (BIST, Scan, JTAG)
  • CAD Experience: Synopsys preferred , Cadence acceptable

 

 

Experienced DFT Engineer

Requirements:

 

  • BSc. in Electrical Engineering (from known university)
  • Minimum 3 years of experience on DFT – Must!

 

Knowledge and experience in:

 

  • Knowledge and experience with DFT methodologies (Scan, ATPG, @speed, memory BIST, I/O DFT)
  • Scan insertion and ATPG experience for stuck-at, transition delay, bridging and IDDQ
  • Coverage improvement and DFT DRC analysis using FTMAX / DFTCompiler / TetraMAX / SpyglassDFT - Memory BIST using Tessent MBIST (MentorGraphics)
  • Strong knowledge of JTAG 1149.1, 1149.6 and P1500 standards
  • Hands on design and implementation experience in DFT features
  • In depth understanding of DFT tool flows and methodologies (Synopsys or mentor or any other equivalent tools).Mentor Tessent MBIST experience is an added advantage
  • Hands on experience in end to end design flow (conception to TO to production) in DFT
  • Experience using Perl or other UNIX scripting languages for flow automation
  • Experience with Formal equivalence checking
  • Experience with setting up and running gate level simulations

 

 

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972.9.7780273