Experience Verification Engineer  

Requirements:

  • 5 years of SoC System Verilog validation experience.

  • Hands on experience using UVM to verify ASICs.

  • Advanced knowledge of System Verilog test-bench language.
  • Experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations, formal validation.

 

Preferred Requirements:

  • Experience with the full digital design verification cycle -- from spec through bring-up and prototyping and debug systems.
  • Experience with performance, power validation, digital design (RTL), and formal verification.
  • Experience with SOC design in DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, and ARC CPU
  • Experience with mixed signal verification methodology for IPs such as PHY’s, A2D, PLLs etc.
  • Experience with software and C/C++ for reference model development. Developed drivers for ARM SoC IP’s.

 

 

 

Experience RTL designer

Requirements:

  • 5 years hands-on System Verilog RTL coding.

  • Experience with tools such as VCS, Verdi, and Spyglass.
  • Experience debugging and working with validation using UVM.
  • Experience with Multiple Clock Domains, multiple power domains, low power design.

 

Preferred Requirements:

  • Experience with SoC design in DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, and ARC CPU
  • Experience with clock crossing interface like Gray FIFO, CDC.
  • Experience with Pre silicon Validation, UVM codding, Validation tools and methodology.
  • Experience in Full design cycle including BE design, Synthesis, Static Timing, floor planning, DFT integration.
  • RTL for FPGA and emulation
  • Experience with software and with C/C++ for reference model development. Developed drivers for ARM SoC IP’s .

 

 

 

Embedded IP’s software driver’s development Engineer

Requirements:

  • 5 years of writing embedded drivers for SoC IP’s.
  • Strong C/C++ programmer (able to write correct and efficient code quickly, and be great at debugging low-level drivers)
  • Experience developing drivers for ARM CPU, memory controllers, AMBA buses, caches, peripheral IP’s etc.) 
  • Experience with Linux, Android embedded operating systems.
  • Experience in system power up enabling and debugging.
  • At least 3 years of SoC System Verilog validation experience. Hands on experience using UVM to verify ASIC’s.
  • Advanced knowledge of System Verilog test-bench language.
  • Experience in development of software to validate SOC systems.

 

 

 

Experienced Back-End Engineer

Requirements:

  • BSc. in Electrical Engineering (from known university)
  • Minimum 2 years of experience – Must!

 

Knowledge and experience in :

  • Floor plan and Place & Route
  • Timing Closure & debug, STA
  • Clock Tree Synthesis
  • Power Grid Analysis
  • LVS/DRC debug
  • Experience with DFT - Advantage
  • Experience with ICC – Advantage
     

 

 

Experienced ASIC Project leader

Requirements:

  • BSc. in Electrical Engineering (from known university)
  • Minimum 5 years of experience – Must!
  • Technical management experience – Advantage

 

Knowledge and experience in:
Floor plan and Place & Route, Block & Top level

  • Timing Closure & debug, STA, SDC insertion and analysis.
  • Clock Tree Synthesis
  • Power Grid Analysis
  • LVS/DRC Debug
  • DFT & ATPG methodologies (BIST, Scan, JTAG)
  • CAD Experience: Synopsys preferred , Cadence acceptable

 

 

 

Experienced DFT Engineer

Requirements:

  • BSc. in Electrical Engineering (from known university)
  • Minimum 3 years of experience on DFT – Must!

 

Knowledge and experience in:

  • Knowledge and experience with DFT methodologies (Scan, ATPG, @speed, memory BIST, I/O DFT)
  • Scan insertion and ATPG experience for stuck-at, transition delay, bridging and IDDQ
  • Coverage improvement and DFT DRC analysis using FTMAX / DFTCompiler / TetraMAX / SpyglassDFT - Memory BIST using Tessent MBIST (MentorGraphics)
  • Strong knowledge of JTAG 1149.1, 1149.6 and P1500 standards
  • Hands on design and implementation experience in DFT features
  • In depth understanding of DFT tool flows and methodologies (Synopsys or mentor or any other equivalent tools).Mentor Tessent MBIST experience is an added advantage
  • Hands on experience in end to end design flow (conception to TO to production) in DFT
  • Experience using Perl or other UNIX scripting languages for flow automation
  • Experience with Formal equivalence checking
  • Experience with setting up and running gate level simulations

 

 

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972.9.7780273