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Milandr started our collaboration with Avnet ASIC Israel LTD (AAI) in 2011. 
During this period, we realized 2 projects where AAI was the chip  integrator, doing all backend design. 
Our company’s Design Center developed a power control unit and a RC oscillator block of  IC  in accordance with AAI spec. 
The first project is already silicon proven, and works well. 
Now we are working on next collaborative design, where our companies play same roles.
We have found AAI team to be highly professional, experienced and extremely efficient in their technical abilities.
We consider AAI a highly competent integrator of the complex digital-to-analog VLSI chips and appreciate their ability to accurately formulate the spec for system sub-blocks (including analog ones), promising 100% guaranteed success of the project.

Michael Kakoulin
Head of IC Design Centre
Milandr, Russia

Cadence design systems will cooperate with Avnet ASIC Israel (AAI). Sunday October 15th, 2006, 12:48, Guy Grimland

Avnet ASIC Israel (AAI) design platform will be based on Cadence tools

In the framework of the cooperation between Cadence Design Systems and Avnet ASIC Israel, the latter announced that its design platform would be based on Cadence tools. This collaboration will enable AAI to support new Fabless companies, which do not possess CAD infrastructure and engineering resources, while shortening their time-to market and minimizing chip development costs.

"The new agreement with Cadence allows us to establish an efficient development platform which will support extensive number of designs and hierarchies, saving time and costs for us and consequently our customers. Cadence platform enables us to successfully manage the challenges of advanced deep sub-micron processes, such as 90 nm and under, and complex multi-million gate SoC designs. In addition, the new agreement will enable AAI to respond to market demands, especially consumer goods market, which requires high performance, low energy consumption, high reliability rate of the products and low costs", - said Nadav Ben-Ezer.

Gidon Kedem, CEO of Cadence Israel said: "The combination of our advanced CAD tools and our agreement with AAI, as well as our relationships with IP and silicon vendors in Israel and worldwide, provides our customers with all the necessary tools to accomplish the entire process from originating design idea to mass production ramp up, in the coherent and matched environment".

Hebrew Version:

קיידנס דיזיין סיסטמס תשתף פעולה עם אבנט אייסיק
יום ראשון, 15 באוקטובר 2006, 12:48 מאת: גיא גרימלנד,

אבנט תבסס את תהליך התכנון שלה על כלי התכנון של קיידנס

במסגרת שיתוף פעולה בין קיידנס דיזיין סיסטמס ואבנט אייסיק, האחרונה הודיעה כי מעתה, תבסס את תהליך התכנון שלה על כלי התכנון של קיידנס.

שיתוף הפעולה יאפשר לחברות Fabless (חברות המפתחות שבבים ואינן מייצרות אותם) צעירות להאיץ את זמן ההגעה לשוק ולהפחית את עלות פיתוח השבבים. אבנט מציינת כי גם חברות ותיקות וגדולות העוסקות בתחום פיתוח רכיבים, שלהן תשתיות כוח אדם וכלי CAD משלהן, יוכלו ליהנות משירותים אלו בפרויקטים שהן בדרך כלל מוציאות לקבלנים חיצוניים.

"ההסכם החדש עם קיידנס מאפשר לנו להקים פלטפורמת פיתוח יעילה, לתמוך במספר רב של תכנונים והירארכיות ולקצר את תהליכי הפיתוח על ידי מקבול התהליכים והתכנסותם במהירות. השימוש בסביבת הפיתוח של קיידנס מאפשר לנו להתמודד בהצלחה עם האתגרים שמציבים תהליכי ייצור מתקדמים של 90 ננו-מטר ופחות, וצפיפויות של 10 מיליון ויותר שערים לוגיים, תוך עמידה בדרישות השוק, ובמיוחד שוק מוצרי הצריכה, לביצועים גבוהים, צריכת הספק נמוכה, מזעור גודל פיסת הסיליקון ואמינות הייצור, כדי לחסוך בעלויות המוצרים לצרכנים", ציין נדב בן עזר, מנכ"ל אבנט אייסיק ישראל.

גדעון קדם, מנכ"ל קיידנס ישראל, ציין כי "בשילוב ההסכמים שיש לנו עם ספקי IP ויצרני סיליקון בארץ ובעולם, לקוחותינו יכולים כעת לבצע את כל התהליך המורכב של מעבר מגיבוש הרעיון התכנוני לייצור בכמויות גדולות, בסביבה קוהרנטית ומתואמת".

AAI created an ASIC design that was instrumental in helping Samsung to launch the first-ever cell phones and personal digital assistants supporting WiBro technology. WiBro provides wireless broadband on the go, offering access at speeds of up to 30 megabits per second. These communications products were introduced at the 2005 APEC summit in Korea. The APEC summit is a premier forum for facilitating economic growth, cooperation, trade and investment in the Asia-Pacific region. It is attended by political and economic leaders from numerous countries.
Samsung's Appreciation Plaque to Avnet ASIC Israel, AAI, Nadav Ben-Ezer and Eugene Lyubinsky

"We deeply appreciate that you overcame all obstacles to success and completed a task of great difficulty with a flash of wit and so eventually contributed to a great successful demonstration in APEC 2005 Korea. We wish your company's eternal development and prosperity, and we also pour our whole heart in this plaque of appreciation. Samsung Electronics".
"The Mobileye EyeQ System-on-Chip (SoC) offers a solution for computationally intensive, real-time visual recognition and scene interpretation applications that can be customized for use in intelligent vehicle systems. The chip architecture is designed to maximize cost performance by executing a full-fledged application on a single ultra-low-cost chip. An example of such an application is low-cost Adaptive Cruise Control using a single video source. The EyeQ system detects vehicles, motorcycles, pedestrians, and road markings to provide an intelligent driver-assistance system.
AAI performed for us the RTL to GDSII implementation, as well as RTL development of the 2 ARM CPU and AHB system and IP integration and provided support for testing and package development in 292 HSBGA of an ASIC device with the following specs:
Random gates:  2m Gates
Memories:  2Mbits SRAM with Redundancy, divided in 40 cuts
Major IPs: 2 ARM946 cores with 16KB I-Cache and 16 KB D-Cache, PLL, SDRAM controller, DMA controller, CAN controller, I2C controller and more
Technology:  TSMC 0.18u, 6LM
Performance:  110 Mhz
Package:  292 HSBGA
AAI also supported us with two additional tape-outs; one with several mask changes and the second with full mask changes.
AAI is very professional and familiar with VLSI aspects like front-end design, including the Design For Test (DFT) and the architecture, back-end - including all the physical implementation, after silicon design processes - including testing, packaging and production. They acted as a Mobileye design team for me and worked in complete synchronization with the Mobileye design team."

Elchanan Rushinek
Vice President Engineering

"WisAir is a Fabless company that designs and manufactures VLSI chip sets for Wireless USB applications. We are currently designing a single chip WUSB to be manufactured at TSMC.
Avnet ASIC is performing for us the Netlist to GDSII design flow, including Place & Route, Timing Closure, DFT, Physical verifications and preparations for manufacturing (I/O considerations, ATPG, Package constraints, etc.).

We have selected Avnet ASIC for the following reasons:

We believe that the combination of our unique technology and the expertise and synergy of both our design teams will enable us to reach the market in the shortest time with first-time-working silicon which we will sell next year in high quantities."

Nadav Zalcman
Vice President VLSI
  • Their proven experience and expertise in Deep Sub-Micron SoC designs.
  • The completeness of their Design Flow methodologies based on state-of-the-art Cadence tools.
  • Local support, including same time zone and language, very short response time and the ability to have frequent face-to-face meetings with the design teams to resolve any design issues.
  • The stability of their operation and their reputation as a leading ASIC design center in Israel for many years.