Our customers have the flexibility to choose an entry point into the SoC implementation flow according to their needs, expertise and available CAD environment. Typically, one of the following signoff methods will be selected:

Architecture Specification Signoff

 

The customer prepares the Architecture and Verification requirements of the chip with AAI support. AAI will write the RTL code according to the specifications, will integrate the required IPs and will complete the full RTL to GDSII design flow.

 

 

RTL Signoff

 

The customer will provide a functionally verified synthesizable RTL code of his design and design constraints (performance constraints, IO requirements, supply voltages, technology choice, application environment, etc.). AAI will perform a complete RTL to GDSII design flow according to the design constraints, and will prepare the design for tape-out.

 

 

Netlist Signoff

 

The customer will deliver a fully verified synthesized netlist that is passing gate level simulation and static timing as well as the required design constraints. AAI will do physical implementation of the chip from gate level.

 

 

Design Migrations and Conversions

 

AAI also provides technology migration and conversion services from existing ASIC or FPGA design to ASIC technology. These services involve a different flow beginning at a legacy design netlist, GDSII, libraries and technology. 

 

 

SoC (System-on-Chip) Design Flow

 

 

To assure the quality and timely schedule of the design, an experienced project leader from AAI side is assigned for every project.